In the semiconductor manufacturing, with the development of Ultra-large-scale integrated circuits (VLSI), the characteristics sizes of the integrated circuits are continuously decreasing. Since the transistor size is getting smaller and smaller, and the operating speed is getting faster and faster, the transistor performance requirement in the semiconductor manufacturing process is also getting higher and higher. Carrier mobility is one of the key factors that affects the transistor performance. As such, effectively improving the carrier mobility becomes one of the priorities in the transistor device manufacturing field.
In the fabrication of complementary metal-oxide-semiconductor field effect transistor (CMOS) devices, P-type metal oxide semiconductor (PMOS) field effect transistors and N-type metal oxide semiconductor (NMOS) field effect transistors are generally processed separately. For example, in the manufacturing process for forming a PMOS device, epitaxial growth of germanium silicon (EPI SiGe) process can be used for forming a silicon germanium (SiGe) stress layer in the source and drain (S/D) region of the PMOS device. The SiGe stress layer can apply an appropriate compressive stress to the channel region to improve the hole mobility. Therefore, EPI SiGe process is one important technique in the PMOS device stress engineering. As another example, in the manufacturing process for forming an NMOS device, a stress layer can be formed to provide an appropriate tensile stress to improve the electron mobility.
However, it is hard to improve the performance of the PMOS device formed by the existing manufacturing processes. Further, the processing window is very small, and the product yield is also limited.